NXP Semiconductors /MIMXRT1021 /DMAMUX /CHCFG[6]

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Interpret as CHCFG[6]

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SOURCE0 (A_ON_0)A_ON 0 (TRIG_0)TRIG 0 (ENBL_0)ENBL

A_ON=A_ON_0, ENBL=ENBL_0, TRIG=TRIG_0

Description

Channel index Configuration Register

Fields

SOURCE

DMA Channel Source (Slot Number)

A_ON

DMA Channel Always Enable

0 (A_ON_0): DMA Channel Always ON function is disabled

1 (A_ON_1): DMA Channel Always ON function is enabled

TRIG

DMA Channel Trigger Enable

0 (TRIG_0): Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

1 (TRIG_1): Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

ENBL

DMA Mux Channel Enable

0 (ENBL_0): DMA Mux channel is disabled

1 (ENBL_1): DMA Mux channel is enabled

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